A substrate for semiconductor device using a nitride semiconductor is adopted in, e.g., a power device which operates at a high frequency with high output. In particular, as a device suitable for performing amplification in a high-frequency band of, e.g., micro waves, submillimeter waves, or millimeter waves, for example, a high electron mobility transistor (HEMT) is known.
Such a substrate for semiconductor device which is used as HEMT is disclosed in, e.g., Patent Document 1. In Patent Document 1, as shown in FIG. 13, a substrate for semiconductor device has a buffer layer 114 which is formed on a silicon substrate 111 and formed by alternately stacking first semiconductor layers 112 made of AlN and second semiconductor layers 113 which is made of GaN and doped with Fe, a channel layer 115 which is formed on the buffer layer 114 and made of GaN, and a barrier layer 116 which is formed on the channel layer 115 and made of AlGaN.
It is to be noted that providing a source electrode S, a drain electrode D, and a gate electrode G on the HEMT semiconductor substrate enables obtaining the HEMT.
In the substrate for semiconductor device disclosed in Patent Document 1, a breakdown voltage in a longitudinal direction is improved by doping Fe in the buffer layer 114 (see, e.g., FIG. 12). Here, FIG. 12 shows drain voltage dependence of a leak current in the longitudinal direction in each of a Fe doping example and a non-doping example.
However, in the Fe doping, it is known that precipitous control cannot be performed due to surface segregation or the like and hence Fe is mixed into an upper layer (i.e., the channel layer) (see Patent Document 2). It is known that, when this Fe enters the channel layer, a harmful influence, e.g., a reduction in mobility is exerted on forward characteristics, and adopting a structure and a manufacturing method which can prevent mixing into the channel layer is preferable.
A structure which prevents Fe used for an increase in resistance from being introduced into the upper channel layer is disclosed in, e.g., Patent Documents 2 to 4.